As a conventional liquid crystal display (LCD) device, there has been known an LCD device of the active matrix driven system (hereinafter, referred to as “active matrix driven LCD device”). FIG. 19 shows an active matrix-driven LCD device 100.
The active matrix-driven LCD device 100 has a pixel array ARY, a scan driver GD and a data driver SD.
The pixel array ARY has a plurality of scan signal lines GL, and a plurality of data signal lines SL intersecting the plurality of scan signal lines GL. One pixel is provided in a position surrounded by adjacent two scan signal lines GL and adjacent two data signal lines SL, so that pixels PIX are arranged totally in a matrix form. In synchronization with a timing signal such as a clock signal SCK, the data driver SD samples an input video signal DAT, and amplifies, as required, and supplies the sampled video signal DAT to the data signal lines SL.
The scan driver GD, in synchronization with a timing signal such as a clock signal GCK, selects the scan signal lines GL sequentially to control the turn-on and -off of switching devices within the pixels PIX, whereby the video signal (data) supplied to the data signal lines SL is written to the pixels PIX. The pixels PIX function to retain the data written in the pixels PIX.
FIG. 20 shows details of the pixel PIX. The pixel PIX has a field effect transistor SW as a switching device, and a pixel capacitor CI (made up of liquid crystal capacitor CL and auxiliary capacitor CS, the latter being added as necessary.).
The field effect transistor SW has a drain, a source and a gate. Hereinafter, one of the drain and the source will be referred to as a first electrode and the other of the drain and the source as a second electrode.
The first electrode of the field effect transistor SW is connected to the data signal line SL, and the second electrode is connected to an end “a” of the pixel capacitor CI. Also, the gate of the field effect transistor SW is connected to the scan signal line GL. An end “b” of the liquid crystal capacitor CL is connected to a common electrode line which is common to all the pixels PIX. By a voltage applied to the liquid crystal capacitor CL, the transmissivity or reflectance of the liquid crystals is modulated, and an image is displayed.
In conventional active matrix type LCD devices, an amorphous silicon thin film formed on a transparent substrate of glass or the like is used as a material of the pixel transistor SW. Also, the scan driver GD and the data driver SD in conventional active matrix type LCD devices have been implemented by external integrated circuits (ICs), respectively.
However, these days, to respond to demands for improvement in driving force of pixel transistors to keep up with larger-sized screens, reduction in mounting cost of driver ICs, or for reliability in mounting, pixel arrays and driver circuits are formed monolithically by using a polysilicon thin film.
With a view to realizing even larger screens and further cost reduction of LCDs, there have been attempts to form such devices as field effect transistors with a polysilicon thin film on the glass substrate at process temperatures below the glass distortion point (about 600° C.).
FIG. 21 shows an active matrix type LCD device 200 in which a pixel array and drivers are formed monolithically.
In this active matrix type LCD device 200, a pixel array ARY, a scan driver GD and a data driver SD are mounted on an insulative substrate SUB, and a timing signal generator CTL and a supply voltage generator VGEN are each connected to the scan driver GD and the data driver SD.
The data driver SD receives signals such as a video signal DAT. In FIG. 21, paths along which the video signal DAT and the like are transferred within the data driver SD are depicted in broken line.
The scan driver GD receives signals such as a pulse signal GPS. In FIG. 21, paths along which the pulse signal GPS and the like are transferred within the scan driver GD are depicted in broken line.
As the data driver, there have been known data drivers of the dot sequential drive system and data drivers of the line sequential drive system, differing from each other depending on the method of writing a video signal into video signal lines. In polysilicon TFT panels in which the data driver has been integrated, the data driver of the dot sequential drive system is often used for the sake of configurational simplicity of the data driver.
Now the construction of a typical data driver of the dot sequential drive system is explained with reference to FIG. 22.
FIG. 22 shows a data driver SD of the dot sequential drive system. In the dot sequential drive system, sampling switches AS are opened and closed in synchronization with output pulses from individual stages (latch circuits) of a shift register circuit SFC, which is made up of a plurality of latch circuits LATA, LATB. By the sampling switches AS being opened and closed, a video signal DAT supplied to the video signal line is written into the data signal lines SL.
As shown in FIG. 22, a buffer circuit BFC1 is located between the shift register circuit SFC and the sampling switches AS. The buffer circuit BFC1 fetches a pulse signal output from the shift register circuit SFC, and retains and amplifies the pulse signal and moreover, as required, generates an inverted signal of the pulse signal.
The construction of the scan driver is explained below with reference to FIG. 23.
FIG. 23 shows a scan driver GD. This scan driver GD has a shift register circuit SFC composed of a plurality of latch circuits LATA and LATB, and a buffer circuit BFC2.
The scan driver GD amplifies output pulse signals (or logical operation results with other signals if required) of individual stages (latch circuits) of the shift register circuit SFC, which is composed of the plurality of latch circuits LATA, LATB, and then, outputs the amplified output pulse signals as scan signals.
As described above, both of the data driver SD and the scan driver GD use a shift register circuit SFC for sequentially transferring pulse signals.
FIG. 24 shows a shift register circuit SFC. As shown in FIG. 24, a plurality of latch circuits LATA, LATB are alternately connected to one another in series. In FIG. 24, a start signal ST corresponds to the signal SSP of FIG. 22 and the signal GSP of FIG. 23, and a clock signal CLK corresponds to the signal SCK of FIG. 22 and the signal GCK of FIG. 23.
FIG. 25B shows the clock signal CLK to be supplied to the shift register circuit SFC shown in FIG. 24. In addition to the clock signal CLK, a clock signal/CLK inverted in phase relative to the clock signal CLK is also supplied to the shift register circuit SFC shown in FIG. 24.
FIG. 26 shows the latch circuit LATA forming part of the shift register circuit SFC. FIG. 27 shows the latch circuit LATB forming part of the shift register circuit SFC.
Each of the latch circuit LATA and the latch circuit LATB has one inverter and two clocked inverters CICA and CICB. Clock signals CLK and/CLK opposite in phase to each other are supplied to the two clocked inverters CICA and CICB.
FIG. 28 shows the clocked inverter CICA, and FIG. 29 shows the clocked inverter CICB. For example, in the clocked inverter CICA, when the clock signal CLK is at a high level, an inverted signal of a signal supplied to an input terminal IN of the clocked inverter CICA is output from an output terminal OUT of the clocked inverter CICA. Also, in the clocked inverter CICB, when the clock signal CLK is at a low level, an inverted signal of a signal supplied to an input terminal IN of the clocked inverter CICB is output from an output terminal OUT of the clocked inverter CICB.
It is noted that in referring to a shift register circuit or a latch circuit in the present specification and the accompanying drawings, because clock signals opposite in phase to each other are supplied to those circuits, the description therefor is, in some cases, made by using only one CLK of these clock signals.
In the shift register circuit SFC shown in FIG. 24, because the clock signals CLK, /CLK are supplied to all the latch circuits LATA, LATB, the load of the clock signal lines CLKL, /CLKL becomes extremely large. As a result, external ICs (controller IC and the like) having large driving power need to be used in order to drive the clock signal lines CLKL, /CLKL, which would lead to increase in fabricating costs of the LCD device as well as increase in power consumption of the LCD devices.
Japanese Patent Laid-Open Publication HEI 3-147598 (JP-A-3-147598) discloses an arrangement that only when output of stages (latch circuit) of the shift register circuit is significant (active), the clock signal is supplied to those latch circuits in order to reduce the load of the clock signal lines.
More specifically, it is controlled by output signals of the individual latch circuits (or a sum signal of output signals of a plurality of adjacent latch circuits) whether or not the clock signal line and the latch circuit are disconnected from each other.
However, in such an arrangement, upon power-on, since the internal node state (voltage level) of the shift register circuit is unstable (meaning that the internal node can take any state), it could be the case, in the worst, that all the internal nodes of the shift register circuit go active at the power-on. This state will continue until a signal corresponding to the inactive state scans all the stages of the shift register circuit (i.e., until the shift register circuit is initialized).
Further, in that state, since the clock signal has been supplied to all the latch circuits, the load of the clock signal lines has become extremely large, as compared with the normal state (i.e., a state in which a clock signal is supplied to one to a few latch circuits when one pulse signal scans the shift register circuit).
Therefore, with insufficient driving power (i.e., with the external IC optimized for small load), the clock signal lines could not be driven within a specified time duration, in which case the shift register circuit might be disabled.
Accordingly, the external IC for supplying the clock signal is required to have such power as to enable the driving even for such a large load, whereas in the normal state, the load is small and such a large driving power is unnecessary. That is, the external IC needs to have a large driving power only for the initialization of the shift register circuit upon power-on, which has been an obstacle to an progress toward lower cost and lower power consumption.
Japanese Patent Laid-Open Publication HEI 7-147659 (JP-A-7-147659) discloses a liquid crystal panel driver which drives an LCD device to perform black display in upper and lower parts of its screen. The term “black display” refers to a display as shown in FIG. 32. In this liquid crystal panel driver, based on a vertical synchronous signal Vsync, a timing control circuit generates a gate clock signal GCLK, the frequency of which is same as the clock rate of an input video signal during the video effective period, as shown in FIGS. 33A, 33B and 33C. Meanwhile, during a return period between the video effective periods (vertical scan periods), the frequency of the gate clock signal GCLK is higher than the horizontal synchronous frequency. Then, during the return period, a black level is given to a data driver as a video signal. In this way, necessary black display is performed during a short return period.
As is well known, liquid crystals need to be driven by AC voltage. Therefore, most liquid crystal panel drivers implement the drive by inverting the polarity of a voltage to be applied, every vertical scan line. In the aforementioned liquid crystal panel driver, for implementation of black display for a total of N horizontal lines in an upper black display area located in the upper part of the screen and a lower black display area in the lower part of the screen, the N horizontal lines are scanned during the return period as shown in FIGS. 33A–33C. However, in the case where the voltage to be applied is inverted in polarity every vertical scan line as described above, if the black display area is increased so that the value of N is increased, the frequency of the applied voltage becomes extremely high. In this case, it is difficult to accomplish the polarity inversion every vertical scan line. Thus, in such a case, the applied voltage will have to be inverted every black display area, although this may cause occurrence of flickers.
Each time one vertical scan line is selected, a video signal of the black level voltage is output from the data driver. However, the output time of the black level voltage becomes shorter as N becomes larger, which makes it impossible to write the black level voltage enough into the vertical scan lines. Therefore, for example, whereas a black level voltage sampled by the data driver is written into pixels, as it is, at the first horizontal line out of n horizontal lines of the upper black display area, the sampled black level voltage would gradually decrease at the following horizontal lines so that the black level voltage would largely differ between the first horizontal line and the nth horizontal line. As a result, as shown in FIG. 34, uniform solid black display is not performed in the black display area, but gradations appear.